minimum solder mask silver constraint violation altium
In the above image, the silk to solder mask clearance is defined as 2 mil for the Top Overlay layer; simply create a second PCB design rule for silk to solder resist clearance if you want to add the rule to the Bottom Overlay. Registration is free. You will find this project on GitHub, released under an open-source license if you simply want to grab it to copy and paste into your own design. Ensure areas with very small solder mask slivers are not causing problems during testing. Save the PCB file locally.
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